Integrated circuits (ICs) are built from standard cell circuits such as a NAND gate, NOR gate or an inverter on a semiconductor. Each standard cell circuit is made up of a number of transistors. In order to increase the number of transistors per die, the tools to manufacture integrated circuits employ smaller line widths and scaled down features. Tap cells are made with every standard cell to make connections to the substrate and well. While manufacturing the ICs, the tap cells are typically patterned using lower-resolution litho tools. In case of 28 nm technology node, the tap cells are patterned using 248 nm litho tools. The tap cells are generally pre-placed at a fixed pitch in a logic design block before the other standard cells get placed. The advanced 193 nm litho tool, which is of a higher cost, is used mainly for the critical mask layers and not to pattern the tap cells. In light of the continuing developments in the design and manufacture of integrated circuits, the cell dimensions are shrinking. The tap cells consume the area of the standard cell that may otherwise be available for other cell circuitry and for wires in the cell. The issue apparent is that the tap cells do not scale aggressively with technology nodes when 248 nm litho tools are used. Hence there exists a need to optimize number of transistors per die (area savings) and the cost of producing the ICs.